(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the prevention of copper diffusion into dielectric layers during the formation of damascene copper interconnects in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Copper damascene interconnects are becoming increasingly common in the art of integrated circuit manufacture. Copper interconnects offer a significant advantage over traditional aluminum interconnects because of the lower resistivity of copper. Unfortunately, copper does not etch as easily as aluminum. This fact makes it difficult to fabricate copper interconnects using the traditional deposition and patterning techniques.
Damascene techniques allow copper to be used as the interconnect material. In damascene processes, trenches are first patterned into a dielectric material. Then copper is deposited overlying the dielectric material to fill the trenches. Finally, a polish down operation is performed to remove excess copper and to form the interconnect patterns within the confines of the trenches.
Referring to FIG. 1, a cross-section of a partially completed dual damascene structure in a prior art integrated circuit device is shown. A first dielectric layer 12 overlies a semiconductor substrate 10. A first copper interconnect 18, isolated by a first barrier layer 14, is formed through the first dielectric layer 12. A passivation layer 22 is formed overlying the first dielectric layer 12 and the first copper interconnects 18. A second dielectric layer 26 overlies the passivation layer 22. An etch stopping layer 30 overlies the second dielectric layer 26. A third dielectric layer 34 overlies the etch stopping layer 30. Finally, a cap layer 38 is formed overlying the third dielectric layer 34.
A trench and via trench have been etched in the dielectric layers overlying the first copper interconnects 18. The trench and via extend through both the third dielectric layer 34 and the second dielectric layer 26. In this configuration, the structure is described as dual damascene because, when a copper layer is subsequently deposited and polished down, both the via and the interconnects will be formed at the same time. Note that the passivation layer 22 that overlies the copper interconnect 18 has not been etched at this step in the process.
Referring now to FIG. 2, the passivation layer 22 is etched through to expose the underlying copper interconnect 18. At this point one significant problem in the prior art is demonstrated. To completely etch the passivation layer 22, some over etching must occur. During the over etching, copper material, in the form of elemental copper, copper oxides, and/or copper fluorides, in the copper interconnect 18 is also etched. The copper material that is displaced may then be sputter deposited 42 onto nearby surfaces. Some of the displaced copper is sputter deposited onto the surfaces of the second dielectric layer 26, the third dielectric layer 34, the etch stopping layer 30, and possibly the cap layer 38 as shown by 44.
The sputtered copper 44 would then diffuse into the second dielectric layer 26, the third dielectric layer 34, and, possibly, into the etch stopping layer 30 and the passivation layer 22. A wet or dry cleaning method is typically used to remove the sputtered copper but may still leave some sputtered copper if the cleaning chemistry employed is ineffective.
Referring now to FIG. 3, a barrier layer 46 is deposited overlying the cap layer 38 and filling the trench. The barrier layer 46 is typically composed of a refractory metal or refractory metal nitride. The purpose of the barrier layer 46 is to stop copper out-diffusion from the interconnect trench into the surrounding dielectric material. Unfortunately, if the cleaning method is ineffective, the sputter deposited copper 44 underlies the barrier layer 46. Therefore, further copper out-diffusion into the dielectric material occurs. Finally, a copper layer 50 is deposited overlying the barrier layer 46. The copper layer 50 completely fills the trenches.
Referring now to FIG. 4, the copper layer 50 and barrier layer 46 are polished down to expose the top surface of the cap layer 38. This polish down step removes the excess copper layer 50 to define the second copper interconnect and the via. A second problem is seen herein as significant dishing 54 occurs in the copper layer 50 overlying the trench. The cause of this dishing is the relatively higher polishing rate of the copper layer 50 compared to the barrier layer 46. Removal of all of the barrier layer 46 causes an over polish of the copper layer 50 and the undesirable dishing 54 results.
Several prior art approaches disclose methods to form dual damascene structures in the fabrication of integrated circuits. U.S. Pat. No. 5,821,168 to Jain discloses a process to form dual damascene structures. First, the trench and via are etched through the dielectric layers to the expose the top surface of the underlying copper trace. Second, a barrier layer is formed over the dielectric by nitriding. Third, a silicon adhesion layer is formed overlying the nitrided layer. Finally, copper is deposited and polished down to complete the dual damascene structure. U.S. Pat. No. 5,741,626 to Jain et al teaches a process to use tantalum nitride as an anti-reflective coating in the fabrication of dual damascene structures. U.S. Pat. No. 5,578,523 to Fiordalice et al discloses a process to form dual damascene structures where a polish assist layer is used to prevent dishing during the chemical mechanical polish of the metal layer. U.S. Pat. No. 5,871,572 to Chiang et al teaches a process to form dual damascene structures. U.S. Pat. No. 5,882,996 to Dai discloses a process to etch dual damascene trenches where a stack of photoresist, anti-reflective coating, and photoresist is used to pattern the trenches.